An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA
Published in IEEE Embedded Systems Letters (ESL), 2024
Recommended citation: Yin, X.; Wu, Z.; Li, D.; Shen, C.; Liu, Y. (2024). "An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA." IEEE Embedded Systems Letters, 16(2): 158-161. doi:10.1109/LES.2023.3296507.
Download Paper