Publications

You can also find my articles on my Google Scholar profile.

Journal Articles

Multibit Attention Fusion for Gaze Estimation Using 12-Bit RAW Data From CMOS Sensors

Published in IEEE Transactions on Instrumentation and Measurement (TIM), 2025

Gaze estimation method using multibit attention fusion with 12-bit RAW CMOS sensor data.

Recommended citation: Tian, K.; Wang, H.; Wu, Z.; Lyu, Y.; Vai, M. I.; Liu, Y. (2025). "Multibit Attention Fusion for Gaze Estimation Using 12-Bit RAW Data From CMOS Sensors." IEEE Transactions on Instrumentation and Measurement. doi:10.1109/TIM.2025.3568959.
Download Paper

Accelerating Control Flow on CGRAs via Speculative Iteration Execution

Published in IEEE Computer Architecture Letters (CAL), 2025

CGRA control-flow acceleration via speculative iteration execution.

Recommended citation: Cao, H.; Wu, Z.; Li, D.; Jing, P.; Pun, S. H.; Liu, Y. (2025). "Accelerating Control Flow on CGRAs via Speculative Iteration Execution." IEEE Computer Architecture Letters, 24(1): 109-112. doi:10.1109/LCA.2025.3554777.
Download Paper

HAOT: Heterogeneous Hardware-Aware Tensor Computation Optimization Framework via Transformer

Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025

Hardware-aware tensor computation optimization framework combining learning-based scheduling with analytical hardware modeling.

Recommended citation: Wu, Z.; Wang, H.; Li, N.; Cao, H.; Liu, Y. (2025). "HAOT: Heterogeneous Hardware-Aware Tensor Computation Optimization Framework via Transformer." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. doi:10.1109/TCAD.2025.3629566.
Download Paper

A Flexible Dual-Mode and Efficient RISC-V Coprocessor for On-Node FFT Acceleration in Edge Sensing

Published in IEEE Embedded Systems Letters (ESL), 2025

Dual-mode RISC-V coprocessor design for efficient on-node FFT acceleration in edge sensing.

Recommended citation: Cao, P.; Wang, H.; Cao, H.; Wu, Z.; Liu, Y. (2025). "A Flexible Dual-Mode and Efficient RISC-V Coprocessor for On-Node FFT Acceleration in Edge Sensing." IEEE Embedded Systems Letters. doi:10.1109/LES.2025.3634524.
Download Paper

Design and Implementation of RISC-V System-on-Chip for SPWM Generation Based on FPGA

Published in IEICE Electronics Express (ELEX), 2024

RISC-V SoC design and implementation for SPWM generation on FPGA.

Recommended citation: Yin, Q.; Li, D.; Wu, Z.; Pun, S. H.; Liu, Y. (2024). "Design and Implementation of RISC-V System-on-Chip for SPWM Generation Based on FPGA." IEICE Electronics Express, 21(24): 20240603. doi:10.1587/elex.21.20240603.
Download Paper

SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration

Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024

Partial mapping strategy for CGRAs via sub-CGRA exploration.

Recommended citation: Li, N.; Li, D.; Wu, Z.; Jing, P.; Pun, S. H.; Liu, Y. (2025). "SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 44(7): 2827-2831. doi:10.1109/TCAD.2024.3520024.
Download Paper

An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA

Published in IEEE Embedded Systems Letters (ESL), 2024

FPGA accelerator design for block-sparse CNNs with efficient mapping and execution.

Recommended citation: Yin, X.; Wu, Z.; Li, D.; Shen, C.; Liu, Y. (2024). "An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA." IEEE Embedded Systems Letters, 16(2): 158-161. doi:10.1109/LES.2023.3296507.
Download Paper

HiEval: A Scheduling Performance Estimation Approach for Spatial Accelerators via Hierarchical Abstraction

Published in Journal of Systems Architecture, 2024

Hierarchical-abstraction based scheduling performance estimation for spatial accelerators.

Recommended citation: Wu, Z.; Hu, Y.; Li, N.; Lu, W.; Liu, Y. (2024). "HiEval: A Scheduling Performance Estimation Approach for Spatial Accelerators via Hierarchical Abstraction." Journal of Systems Architecture, 148: 103079. doi:10.1016/j.sysarc.2024.103079.
Download Paper

A Novel Integrated Eye-Tracking System With Stereo Stimuli for 3-D Gaze Estimation

Published in IEEE Transactions on Instrumentation and Measurement (TIM), 2023

Integrated eye-tracking system with stereo stimuli for accurate 3-D gaze estimation.

Recommended citation: Sun, J.; Wu, Z.; Wang, H.; Jing, P.; Liu, Y. (2023). "A Novel Integrated Eye-Tracking System With Stereo Stimuli for 3-D Gaze Estimation." IEEE Transactions on Instrumentation and Measurement, 72: 1-15. doi:10.1109/TIM.2022.3225009.
Download Paper

A Multi-beam Steerable Parametric Array Loudspeaker for Distinct Audio Content Directing

Published in IEEE Sensors Journal (JSEN), 2022

FPGA-based multibeam steerable parametric array loudspeaker enabling distinct audio content directing.

Recommended citation: Wang, H.; Tang, J.; Wu, Z.; Liu, Y. (2022). "A Multi-beam Steerable Parametric Array Loudspeaker for Distinct Audio Content Directing." IEEE Sensors Journal, 22(13): 13640-13647. doi:10.1109/JSEN.2022.3179870.
Download Paper

Conference Papers

FCCQA: A High-Performance FPGA-based Accelerator for Approximate Nearest Neighbor Search

Published in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025

FPGA-based accelerator for approximate nearest neighbor search.

Recommended citation: Miao, T.; Wu, Z.; Li, D.; Lyu, Y.; Vai, M. I.; Liu, Y. (2025). "FCCQA: A High-Performance FPGA-based Accelerator for Approximate Nearest Neighbor Search." Proc. IEEE ISCAS 2025, pp. 1-5. doi:10.1109/ISCAS56072.2025.11043347.
Download Paper

GAS: A Flexible CNN Accelerator Architecture for Heterogeneous Dataflow Implementation

Published in 2025 International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025

Flexible CNN accelerator architecture supporting heterogeneous dataflow implementations.

Recommended citation: Zhang, J.; Li, N.; Wu, Z.; Liu, Y. (2025). "GAS: A Flexible CNN Accelerator Architecture for Heterogeneous Dataflow Implementation." Proc. ISEDA 2025, pp. 52-57.
Download Paper

An Agile Design Method for Reconfigurable Spatial Accelerators in Tensor Computation

Published in 2025 International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025

Agile design methodology for reconfigurable spatial accelerators targeting tensor computation.

Recommended citation: Wu, Z.; Liu, Y.; Li, N.; Cao, H.; Wang, H. (2025). "An Agile Design Method for Reconfigurable Spatial Accelerators in Tensor Computation." Proc. ISEDA 2025, pp. 35-40.
Download Paper

MSCFormer: Multi-Scale Circular Transformer for Image Deblurring

Published in 2024 IEEE International Conference on Visual Communications and Image Processing (VCIP), Tokyo, Japan, 2024

Multi-scale circular attention strategy for image deblurring.

Recommended citation: Wang, S.; Wang, H.; Liu, R.; Wu, Z.; Wei, B.; Liu, Y. (2024). "MSCFormer: Multi-Scale Circular Transformer for Image Deblurring." Proc. IEEE VCIP 2024, pp. 1-5. doi:10.1109/VCIP63160.2024.10849898.
Download Paper

A Novel Predictor With Optimized Sampling Method for Hardware-Aware NAS

Published in 2022 26th International Conference on Pattern Recognition (ICPR), Montreal, QC, Canada, 2022

Predictor with optimized sampling for hardware-aware neural architecture search (NAS).

Recommended citation: Hu, Y.; Shen, C.; Yang, L.; Wu, Z.; Liu, Y. (2022). "A Novel Predictor With Optimized Sampling Method for Hardware-Aware NAS." Proc. ICPR 2022, pp. 2114-2120. doi:10.1109/ICPR56361.2022.9956144.
Download Paper

Wu Zhipeng

Publications

Journal Articles

Conference Papers